A serial peripheral interface (SPI) bus may be used as an interface for communications with a memory device including a NOR cell array. The SPI bus has been suggested by Motorola and is broadly used. The SPI bus is a communication standard between one master device and one or more slave devices, and generally uses a clock frequency of 1 MHz to 100 MHz. A slave device includes a tri-state output terminal, and allows full duplex data communications. A slave device may generally include one clock terminal, one input terminal, one output terminal, and one chip selection terminal.
When an SPI bus is used for a memory including a NOR cell array, the memory may operate as a slave device. In this case, an instruction, an address, and data may be input via one input terminal included in the memory. Since data is read in units of a word or a byte by using a large cell current, a memory including a NOR cell array has a very short random read time. Accordingly, if a read instruction and an address are input to a memory having a NOR cell array via an SPI bus, stored data may be output immediately after the address is completely input.
However, even when an SPI bus is used for a memory including a NOR cell array, if a clock speed is very high, for example, equal to or higher than 70 MHz, data may be output after a predetermined time from when an address is completely input.